The present invention generally relates to the design of field effect transistors (FETS) and, more particularly, to a metal oxide silicon (MOS) transistor structure which facilitates mitigation of undesirable floating body effects, while retaining desirable floating body effects.
As is known in the art, transistors such as metal oxide silicon (MOS) transistors, have been formed in isolated regions of a semiconductor body such as an epitaxial layer which was itself formed on a semiconductor, typically bulk silicon, substrate. With an n-channel MOS field effect transistor (FET), the body is of p-type conductivity and the source and drain regions are formed in the p-type conductivity body as N+ type conductivity regions. With a p-channel MOSFET, the body, or epitaxial layer, is of n-type conductivity and the source and drain regions are formed in the n-type conductivity body as P+ type conductivity regions. It has been suggested that the semiconductor body, or layer, be formed on an insulating substrate, or over an insulation layer formed in a semiconductor substrate. Such technology sometimes is referred to as Silicon-on-Insulator (SOI) technology. Silicon-on-Insulator MOS technologies have a number of advantages over bulk silicon MOS transistors. These advantages include: reduced source/drain capacitance and hence improved speed performance at higher-operating frequencies; reduced N+ to P+ spacing and hence higher packing density due to ease of isolation; and higher xe2x80x9csoft errorxe2x80x9d upset immunity (i.e., the immunity to the effects of alpha particle strikes).
Silicon-on-Insulator technology is characterized by the formation of a thin silicon layer for formation of the active devices over an insulating layer, such as an oxide, which is in turn formed over a substrate. Transistor sources in drains are formed by, for example, implantations into the silicon layer while transistor gates are formed by forming a patterned oxide and conductor (e.g. metal) layer structure. Such structures provide a significant gain in performance by having lower parasitic capacitance (due to the insulator layer) and increased drain current due to floating body charging effects (since no connection is made to the channel region and charging of the floating body provides access towards a majority of carriers which dynamically lower the threshold voltage, resulting in increased drain current). However, the floating body can introduce dynamic instabilities in the operation of such a transistor.
An SOI field effect transistor combines two separated immunity groups, generally formed by implantation, constituting the source and drain of the transistor with the general region (device body) between them covered by a thin gate insulator and a conductive gate. Typically no electrical connection is made to the channel region and therefore the body is electrically floating. Because the source and drain regions normally extend entirely through the thin silicon layer, the electrical potential of the body is governed by Kirchoffs current law, wherein the sum of the currents flowing into the body equals the sum of the currents flowing out of the body. Because the channel potential is dependent on the body voltage, the device threshold voltage varies as a function of the body voltage.
The boundaries between the channel region and the source and drain, respectively, form junctions which are normally reversed biased. Conduction in the channel region normally occurs immediately below the gate insulator in the region in which depletion can be controlled by a gate voltage. However, the junctions at the boundary of the source and drain also form a parasitic lateral bipolar transistor, which, in effect exists somewhat below the field effect transistor and may supplement desired channel current. On the other hand, the parasitic bipolar device cannot be controlled and under some bias conditions, the operation of the parasitic bipolar device may transiently dominate the operation of the field effect transistor and effectively occupy substantially the entire silicon layer at times when the channel current is not desired.
When the device is switching, the body is coupled to various terminals of the device because there are capacitances between the body and gate, body and source, and body and drain respectively. When the voltage at the various terminal changes, the body voltage changes as a function of time which in turn effects the device threshold voltage. In certain cases, this relationship may be harmful to a device (e.g., inverter). For example, when the gate of an inverter is switched on the drain is discharged (which is typically the output of the inverter)xe2x80x94thus the drain voltage falls when the gate is switched ON. Because the drain and body are capacitively coupled, when the drain voltage drops so does the body voltage. There is an inverse relationship between the body voltage and the threshold voltage. For an NMOS device, when the body voltage falls, the device threshold voltage increases. When the body voltage increases the threshold voltage decreases. Thus, the capacitive coupling between the drain and the body results in the device losing drive current as the device is being switched.
In SOI transistors there is a lack of a bulk silicon or body contact to the MOS transistor. In some devices, it is desirable to connect the p-type conductivity body in the case of an n-channel MOSFET, or the n-type conductivity body in the case of a p-channel MOSFET, to a fixed potential. This prevents various hysteresis effects associated with having the body potential xe2x80x9cfloatxe2x80x9d relative to ground. With bulk silicon MOSFETs such is relatively easy because the bottom of the bulk silicon can be easily electrically connected to a fixed potential.
SOI devices also exhibit a kink effect which originates from impact ionization. When an SOI MOSFET is operated at a relatively large drain-to-source voltage, channel electrons with sufficient energy cause impact ionization near the drain end of the channel. The generated holes build up in the body of the device, thereby raising the body potential. The increased body potential reduces the threshold voltage of the MOSFET. This increases the MOSFET current and causes the so-called xe2x80x9ckinkxe2x80x9d in SOI MOSFET current vs. voltage (I-V) curves.
With regard to the lateral bipolar action, if the impact ionization results in a large number of holes, the body bias may be raised sufficiently so that the source region to body p-n junction is forward biased. The resulting emission of minority carriers into the body causes a parasitic npn bipolar transistor between source, body and drain to turn on, leading to loss of gate control over the MOSFET current.
One way to eliminate floating body effects of an SOI MOSFET device is to couple the body or bodies to ground for an npn MOSFET device or to couple the body or bodies to VDD for a pnp MOSFET device. However, MOSFET devices with bodies tied to a fixed potential do not perform as well as MOSFET devices with floating bodies. In view of the above, it is apparent that there is a need in the art for a device which mitigates some of the negative effects mentioned above, relating to floating body effects, while retaining the beneficial attributes of floating body effects.
The present invention provides for a system and method for limiting the charge level on a body of an SOI MOSFET device at or below a threshold level. The body of the SOI MOSFET device floats when it is at a charge level below the threshold level. However, the body is coupled to a fixed voltage reference upon reaching the threshold level of the MOSFET device. The body of the MOSFET device will discharge excess charge into the fixed voltage reference. The body is then disconnected from the fixed voltage reference allowing for the body to return to its floating state. The device of the present invention mitigates some of the aforementioned problems associated with floating body effects of MOSFET devices, while retaining the benefits associated with floating body effects.
The present invention employs a charge limiting system that maintains the charge level of the body for a multiple MOSFET device structure. The multiple MOSFET device include a number of bodies linked to one another or a single body, such as a well, being employed for all devices. The single body or bodies are provided with at least one contact that extends to another layer, so that the body can be coupled to the charge limiting system. The charge limiting system includes a charge detector system that monitors the charge level on the body or bodies and a switching system for coupling the body or bodies to a fixed potential, if the charge level of the body or bodies reaches an unacceptable level. The switching system couples the body or bodies to ground for an npn type transistor and to VDD for pnp type transistors. The charge limiting system can include a timing device, so that the body can be coupled to the fixed potential for a predetermined period of time even after the charge level of the body or bodies falls below the threshold value. This ensures that the charge level on the body is sufficiently discharged.
One aspect of the invention relates to a system for limiting the charge on at least one body of at least one transistor device on an SOI MOSFET structure. The SOI MOSFET structure includes a contact coupled to the at least one body. The system comprises a charge detector system adapted to measure the charge on the at least one body via the contact and transmit a signal in response to a charge measurement above a threshold level. The system further comprises a switch system adapted to receive the signal and connect the at least one body via the contact to a fixed reference voltage.
Another aspect of the invention relates to a method of limiting the charge on at least one body of at least one transistor device on an SOI MOSFET structure. The method comprises the steps of monitoring the charge on the at least one body to determine a charge level of the at least one body and connecting the at least one body to a fixed reference voltage, if the charge level on the at least one body is above a threshold level.
Yet another aspect of the invention relates to a system for limiting the charge on a plurality of linked bodies of a plurality of transistor devices on an SOI MOSFET structure. The system comprises a connector coupled to at least one of the plurality of linked bodies and a charge detector system coupled to the contact. The charge detector system is adapted to measure the charge on the at least one body via the contact and transmit a signal in response to a charge measurement above a threshold level. The system further comprises a switch system adapted to receive the signal and connect the at least one body via the contact to a fixed reference voltage.
Another aspect of the invention relates to a system for limiting the charge on at least one body of at least one transistor device on an SOI MOSFET structure. The SOI MOSFET structure includes a contact coupled to the at least one body. The system comprises means for monitoring the charge on the at least one body to determine a charge level of the at least one body and means for connecting the at least one body to a fixed reference voltage, if the charge level on the at least one body is above a threshold level.
To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.